This invention relates to integrated circuits and more particularly to a circuit for configuring an integrated circuit to operate in one or more of a number of different modes of operation.
Integrated circuits (ICs) are typically required to operate in a variety of different modes. For example, microprocessors may be configured to run in either high speed or low speed mode, or alternatively, high power or low power mode. Other ICs, such as analog ICs, may be configured to one of a number of modes to change the characteristics of the device. For example, mode selection in an analog system may change the type of signal processing carried out by the analog system or it may change the internal electrical characteristics of the individual analog functional blocks.
Conventional mode selection circuits are typically implemented using alterable memory structures such as DRAM, SRAM, EEPROM, or Flash, which are integrated on a single semiconductor chip with other portions of an IC. One problem with such structures is that they require special semiconductor processing technologies that may not be readily available or otherwise may increase manufacturing cost. Moreover, the required circuitry for programming such memory structures consumes silicon area, resulting in further increase in cost.
Another conventional method for implementing mode selection consists of hardwiring a device pin to either supply or ground. However, this technique has the disadvantage of only allowing for two modes per pin. Therefore, unless multiple pins are used, only two modes will be available. The use of multiple pins to implement additional modes increases packaging costs as well as the size of the IC.
In some classes of electronic systems, the size and cost of the ICs can be critical and must be minimized. Accordingly, the manufacturing process must be simple and the method of mode selection must be direct. Thus, a simple and cost effective mode selection circuit technique capable of selecting one of at least three operating modes, and which can be implemented in simple or complex process technologies is desired.
In accordance with the present invention a mode select circuit includes a voltage level encoder and a mode select terminal capable of being selectively coupled to one or more of a plurality of configuration elements to bias the mode select terminal to one of a plurality of predesignated voltages. The voltage level encoder is coupled to the mode select terminal for providing one of a plurality of voltage level codes on a plurality of voltage level encoder output terminals in response to the mode select terminal being biased to a corresponding one of the plurality of predesignated voltages.
In one embodiment, the mode select circuit further includes a bias circuit coupled to the mode select terminal for biasing the terminal to one of the predesignated voltages when the mode select terminal is not coupled to any of the configuration elements.
In another embodiment, each of the plurality of voltage level codes configures a first integrated circuit to operate in a respective one of a plurality of operating modes.
In another embodiment, the mode select circuit is in the first integrated circuit.
In another embodiment, the mode select circuit is housed in a second integrated circuit coupled to the first integrated circuit.
In another embodiment, the configuration elements are external to an integrated circuit in which the mode select circuit is housed.
In another embodiment, the voltage level encoder comprises a plurality of voltage detectors each having a trip point, the trip points of the voltage detectors being offset one from another to define a plurality of voltage ranges. Each of the plurality of predesignated voltages is within a respective one of the plurality of voltage ranges.
In another embodiment, the mode select circuit further includes a first power supply terminal for receiving a power supply voltage source and a second power supply terminal for receiving a reference potential, the trip point of each of the voltage detectors being maintained across a range of voltages closer to the ground potential than the power supply voltage.
In yet another embodiment, a mode select circuit includes a bias circuit and a voltage level encoder. The mode select circuit further includes a mode select terminal capable of being selectively coupled to one or more of a plurality of configuration elements to bias the mode select terminal to one of a plurality of predesignated voltages. The bias circuit is coupled to the mode select terminal for biasing the terminal to one of the predesignated voltages when the terminal is not coupled to any of the configuration elements. The voltage level encoder includes a plurality of comparators each having a first input terminal coupled to the mode select terminal and a second terminal coupled to one of a plurality of reference voltages. The voltage level encoder provides one of a plurality of voltage level codes on a plurality of voltage level encoder output terminals in response to the mode select terminal being biased to a corresponding one of the plurality of predesignated voltages.
In another embodiment, he mode select circuit further includes a first power supply terminal for receiving a power supply voltage source, a second power supply terminal for receiving a reference potential, and a plurality of resistors serially connected between the first and second power supply terminals. An intermediate node between every two adjacent resistors provides the plurality of reference voltages.
In another embodiment, each of the serially connected resistors defines a voltage range, each of the plurality of predesignated voltages being within a respective one of the plurality of voltage ranges.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.